IBM Bolsters Custom Chip Capabilities With High-Performance PowerPC 405 Core and Memory Compression Technology
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Fishkill, N.Y (October 14, 1998) – IBM today announced the addition of a new PowerPC 405 embedded processor core to its Blue Logic “core library.” The company also added a unique code compression system to its PowerPC lineup that enables a significant reduction in memory requirements, providing savings on overall system costs.
As a key element of the company’s strategic PowerPC architecture, the PowerPC 405 is an important addition to IBM’s library of chip “cores.” Cores are individual chip designs that can be quickly integrated with other designs to create custom chips. Embedded processors, like the PowerPC 405, are special function microprocessors designed to carry out specific tasks and can be combined with other functions to create “systems” on a single chip.
The PowerPC 405 core, in conjunction with IBM’s existing custom logic offerings, will enable customers to develop smaller, more powerful and less costly products for a broad range of applications, including devices that connect to the Internet.
The tiny, two square millimeter PowerPC 405 processor core, manufactured in IBM’s advanced 0.25 micron technology, operates at speeds of up to 200MHz. This highly versatile core is suitable for both low cost and highly complex communications, imaging and consumer electronics applications and serves as an easy upgrade to designs using IBM’s existing PowerPC 401 microprocessor core.
“IBM’s custom chip business is aggressively focused on strengthening our custom logic offerings to enable products for the networked world,” said Ron Tessitore, IBM director of PowerPC embedded processor solutions. “The PowerPC 405 is a strong addition to our lineup of Blue Logic processor cores customers can now access. It will also become the basis for a versatile family of integrated, customized embedded processors.”
IBM also announced the CodePack memory compression system for PowerPC, a first-of-its-kind compression technology that reduces instruction code size by approximately 40 percent in typical applications. This feature is particularly useful for customers designing extremely cost-sensitive products, such as consumer electronics devices. It enables customers to meet system design and performance needs at lower cost by requiring less memory to perform the same level of function.
Unlike other solutions, CodePack retains the full instruction set, implements a customizable compression algorithm, and requires no significant changes to development tools, with minimal impact on performance. CodePack works by compressing 32-bit instructions to smaller, variable length instructions by means of a software utility run after compiling source code. The software utility will work with standard embedded PowerPC compilers and IBM is working with a number of industry leading vendors, including MetaWare Incorporated and Diab Data, Inc., to integrate the utility into their compiler tools for enhanced function.
Technical Information on the PowerPC 405
The PowerPC 405, operating at up to 200MHz, dissipates as little as 400 milliwatts of power. The 405 core also includes a number of new features which enhance the performance and versatility of the device. For example, the multiply-accumulate (MAC) unit completes a MAC operation in two cycles, providing high performance integer arithmetic for DSP applications such as soft modems and disk drive controllers. In addition, there are four highly functional interfaces on the PowerPC 405 core which enable customers to define both low cost and highly complex custom products. Those interfaces support attachment of co-processors and on-chip memory, as well as provide a high performance communications path to the IBM standard on-chip bus architecture. Finally, the PowerPC 405 core has additional hardware breakpoints and enhanced trace debug logic to assist developers of highly integrated systems on a chip.
Source: IBM